| bio | website | stackoverflow.com/users/… |
|---|---|---|
| location | San Jose, CA | |
| age | 27 | |
| visits | member for | 6 months |
| seen | May 20 at 14:54 | |
| stats | profile views | 4 |
Professional ASIC engineer with experience in RTL design, Verilog, synthesis, power, and timing issues on billion+ gate ICs.
Other hobbies include:
- Computer Graphics
- Android Programming
- C++ Programming
Personal released projects:
| 5 | Mar 6 | ||||||||
| |||||||||
| 12 | Feb 9 | ||||||||
| |||||||||
| 5 | Jan 15 | ||||||||
| |||||||||
| 15 | Dec 11 '12 | ||||||||
| 15 | Dec 8 '12 | ||||||||
| 10 | Dec 7 '12 | ||||||||
| 40 | Dec 5 '12 | ||||||||
| 20 | Dec 4 '12 | ||||||||
| 25 | Nov 22 '12 | ||||||||
| 5 | Nov 11 '12 | ||||||||
| 127 | Nov 6 '12 | ||||||||

