I'm currently creating a CPU in Minecraft just to prove to myself that I can. As part of it, I have 16 bytes of RAM, made with vertical one-block-wide tileable RS-NOR latches.
I currently have this (Minecraft NBT structure file) design for an output bus for this RAM that works fairly well, and fairly quickly.
Let this be the "left" side (with the bit inputs numbered) Let this be the "front" side (with the bit outputs numbered) Let this be the "back" side (with the bit inputs numbered) Note that in all three cases, the numbers are on the block below the power-receiving/giving block.
Links are chained like this:
The big arrow is the direction of data flow (i.e. "forward"), while the little ones are the left-side repeaters that you saw before.
Each bit from the left is OR'ed with the correspondingly-numbered bit from behind; the output goes out the front into the behind of the next link.
Currently my design works well and only takes a few ticks per link. However, I have a semi-slow computer, and I've found that when there are 16 of these links in a row, things get a bit wonky. If I hit a lag spike, sometimes a piston will think it received a 1-tick pulse, and fail to retract its block, which turns on its output bit permanently, adding bits to the ultimate output that shouldn't be there. (That piston is not the only one that fails to retract, all of them do it, seemingly randomly.)
If a new design is the best way to fix this, I need it to fulfill the following:
- It cannot have any extra blocks on the front, left, or back sides. (Right, top, and bottom are fair game)
- It must be 11 blocks long along the forward-backwards axis
- The 0th left input must point directly into the same block that the 0th output points out of
- The inputs and outputs must still be adjacent to each other the way they are now
- Ideally, no pistons are involved, so that no stray 1-tick pulses can mess anything up
Can I fix this sporadic 1-ticking? Or is there a better design that meets the requirements above?