Tim
Professional ASIC engineer with experience in RTL design, Verilog, synthesis, power, and timing issues on billion+ gate ICs.
Other hobbies include:
- Computer Graphics
- Android Programming
- C++ Programming
Personal released projects:
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San Jose, CA
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Member for 8 years, 2 months
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14 profile views
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Last seen Mar 1 '20 at 13:45
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