Timeline for How can I make a fast RAM output bus with no moving parts?
Current License: CC BY-SA 4.0
7 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Aug 21, 2020 at 18:57 | vote | accept | AbyxDev | ||
| Aug 21, 2020 at 18:57 | answer | added | AbyxDev | timeline score: 0 | |
| Aug 3, 2020 at 8:47 | comment | added | SF. | Yes, there's even a way to use 0 pistons per bit except for the final output of the entire bus. See the paragraph on pulse logic on the wiki, and the examples near the end of the page. You'd probably need to redesign a bit of logic, as your fundamental basic operation is now XOR instead of OR, but as long as you read only one memory bank at a time and deactivate the prior one before activating another, it makes no difference. Pulse logic, due to to use of rails (activator and powered) allows some deep compacting. | |
| Aug 2, 2020 at 11:00 | comment | added | AbyxDev | @SF. I set a bunch of repeaters to 2 ticks and added some 2-tick repeaters (MC NBT), but the issue persists because there are 2 pistons in sequence on most bits. 2-ticking the first fixes it, but its 0-tick retraction 1-ticks the second. Your "embracing" option is elegant but is not proof against bitflips from 1-ticks in the inputs. Is there a way to use at most 1 piston per bit? | |
| Jul 27, 2020 at 12:10 | comment | added | SF. | Instead of fighting the block dropping behavior, consider embracing it. Or just set repeaters to 2 ticks. | |
| Jul 25, 2020 at 17:36 | review | First posts | |||
| Jul 26, 2020 at 4:50 | |||||
| Jul 25, 2020 at 17:33 | history | asked | AbyxDev | CC BY-SA 4.0 |